基于FPGA的LCD&VGA控制器设计

port(clk_seq : in std_logic；

rst_seq : in std_logic;

lcd_hs_out : out std_logic;

lcd_dataen : o

lcd_vs_out : out std_logic;

pix_clk : out std_logic );

end seq_gen;

architecture rtl_seq_gen of seq_gen is

signal lcd_hb : std_logic;

signal lcd_hs : std_logic;

signal lcd_vb : std_logic;

signal lcd_vs : std_logic;

signal clken_vcount : std_logic;

begin

hcount: block

signal hcountreg :std_logic_vector(9 downto 0);

signal hz_temp : std_logic;

signal lcd_hz : std_logic;

begin

process (clk_seq,lcd_hz)

begin

if (lcd_hz = '1') then

hcountreg <= (others =>'0');

elsif clk_seq'event and clk_seq = '1' then

hcountreg <= hcountreg +1;

end if;

end process;

lcd_hb <= '0' when hcountreg >=600 and hcountreg < 650

else '1';

lcd_hs <='0' when hcountreg >=治理发愣功 and hcountreg < 630

else '1';

hz_temp <= '1' when hcountreg = 650 else '0';

lcd_hz <=hz_temp or rst_seq;