基于FPGA的LCD&VGA控制器设计

diff : block

signal inputrega : std_logic;

signal inputregb : std_logic;

begin

process(clk_seq)

begin

if clk_seq'event and clk_seq='1' then

inputregb <= inputrega;

inputrega <= not lcd_hs;

end if;

end process;

clken_vcount <= not inputregb and inputrega;

end block diff;

vcount : block

signal vcountreg : std_logic_vector(9 downto 0);

signal lcd_vz : std_logic;

begin

process (clk_seq,lcd_vz)

begin

if(lcd_vz='1')then

vcountreg <= (others => '0');

elsif clk_seq'event and clk_seq = '1' then

if clken_vcount = '1' then

vcountreg <= vcountreg +1;

end if;

end if;

end process;

lcd_vb <= '0' when vcountreg >=600 and vcountreg < 615

else '1';

lcd_vs <='0' when vcountreg >=607 and vcounreg < 治理发愣功

else '1';

vz_temp <= '1' when vcountreg = 615 else '0';

lcd_vz <= vz_temp or rst_seq;

end block vcount;

pix_clk <=clk_seq;

lcd_dataen <=lcd_hb and lcd_vb;