多状态机的协同设计

多状态机的协同设计(第2页)就显得必要了。导出VHDL模型块到ISE中进行仿真后综合,这里就不多讲了，以下是产生的代码：
--  D:\XILINXTUTORIAL\DUOZTJI.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY ieee;
USE ieee.std_logic_unsigned.all;

ENTITY SHELL_DUOZTJI IS
 PORT (CLK,RESET: IN std_logic;
  dcounter0,dcounter1 : OUT std_logic);
 SIGNAL BP_dcounter0,BP_dcounter1,readcounter0,readcounter1: std_logic;
END;

ARCHITECTURE BEHAVIOR OF SHELL_DUOZTJI IS
 SIGNAL sreg : std_logic_vector (1 DOWNTO 0);
 SIGN

AL next_sreg : std_logic_vector (1 DOWNTO 0);
 CONSTANT m0full : std_logic_vector (1 DOWNTO 0) :="00";
 CONSTANT m0writewait : std_logic_vector (1 DOWNTO 0) :="01";
 CONSTANT STATE0 : std_logic_vector (1 DOWNTO 0) :="10";
 CONSTANT write0 : std_logic_vector (1 DOWNTO 0) :="11";

 SIGNAL sreg1 : std_logic_vector (1 DOWNTO 0);
 SIGNAL next_sreg1 : std_logic_vector (1 DOWNTO 0);
 CONSTANT m0empty : std_logic_vector (1 DOWNTO 0) :="00";
 CONSTANT m0readwait : std_logic_vector (1 DOWNTO 0) :="01";
 CONSTANT read0 : std_logic_vector (1 DOWNTO 0) :="10";
 CONSTANT STATE1 : std_logic_vector (1 DOWNTO 0) :="11";

 SIGNAL next_BP_dcounter0,next_BP_dcounter1,next_readcounter0,
  next_readcounter1 : std_logic;
 SIGNAL BP_dcounter : std_logic_vector (1 DOWNTO 0);
 SIGNAL dcounter : std_logic_vector (1 DOWNTO 0);
 SIGNAL readcounter : std_logic_vector (1 DOWNTO 0);
BEGIN
 PROCESS (CLK, next_sreg, next_BP_dcounter1, next_BP_dcounter0)
 BEGIN
  IF CLK='1' AND CLK'event THEN
   sreg <= next_sreg;
   BP_dcounter1 <= next_BP_dcounter1;
   BP_dcounter0 <= next_BP_dcounter0;
  END IF;
 END PROCESS;

 PROCESS (CLK, next_sreg1, next_readcounter1, next_readcounter0)
 BEGIN
  IF CLK='1' AND CLK'event THEN
   sreg1 <= next_sreg1;
   readcounter1 <= next_readcounter1;
   readcounter0 <= next_readcounter0;
  END IF;
 END PROCESS;

 PROCESS (sreg,sreg1,BP_dcounter0,BP_dcounter1,readcounter0,readcounter1,
  RESET,BP_dcounter,readcounter)
 BEGIN
next_BP_dcounter0 <= BP

《多状态机的协同设计(第2页)》