用Verilog HDL实现I2C总线功能

send_byte_num=send_byte_num+1;

end

delay_1: //延时三个周期

begin

if(delay_counter>=2)

send_byte_zt=sendbit2;

delay_counter=0;

end

else

begin

delay_counter=delay_counter+1;

send_byte_zt=send_byte_zt;

end

end

sendbit2:

begin

tempsc1=0; //SCL置零

send_byte_zt=delay_2;

end

delay_2: //延时三个周期

begin

if(delay_counter>=2)

begin

send_byte_zt=sendbit3;

delay_counter=0;

end

else

begin

delay_counter=delay_counter+1;

send_byte_zt=send_byte_zt;

end

end

sendbit3: //判断是否字节中所有位都发送完毕

begin

if(send_byte_num<=8)

begin

send_byte_zt=sendbit1;

end

else

begin

send_byte_zt=ForACK1;

send_byte_num=0;