EDA技术在智能晶闸管触发电路中的应用

ENDpulse;

ARCHITECTUREaOFpulseIS

signalout1,out2:std_logic;

signalcount1,count2:std_logic_vector(7downto0);

BEGIN

begin

IFsyn_output1='0'THEN

count1<="11111110";

out1<='0';

elsif(clk2'eventandclk2='1')then

count1<=count1－1;

if(count1>pulse_data)then

out1<='0';

else

out1<='1';

count1<="00000000";

endif;

endif;

ENDPROCESSpulse_generator1;

pulse_generator2:process(clk2)

begin

IFsyn_output2='1'THEN

count2<="11111110";

out2<='0';

elsif(clk2'eventandclk2='1')then

count2<=count2－1;

if(count2>pulse_data)then

out2<='0';

else

out2<='1';

count2<="00000000";

endif;

endif;

ENDPROCESSpulse_generator2;

enda;

    2．2 PULSE_ASSIGN模块

此模块完成补脉冲形成及脉冲分配功能。为了保证整流桥合闸后共阴极组和共阳极组各有一晶闸管导电，必须对两组中应导通的一对晶闸管同时发触发脉冲。例如当要求VT1导通时，除