Trimedia DSP芯片JTAG接口的仿真器设计

else

data_reg<=data_reg;

end if;

end if;

End process;

Begin

if(nAddrstb'event and nAddrstb='1')then

if(nWrite='1')then

addr_reg<=data;

else

addr_reg<=addr_reg;

end if;

end if;

End process;

下面为发送数据的VHDL例程：（由于接收例程类似发送例程，故省略。）

tms_tdi_write:process(data_flag,oscnm_true)

Begin

if(oscnm_true'event and oscnm_true='1')then

if(nreset='1')then

tmsjtag<=';

end if;

if(data_flag='1')then

if(data_tms_counter="0001")then

tmsjtag<=addr_reg(0);

tdijtag<data_reg(0);

elsif(data_tms_counter="0010")then

tmsjtag<=addr_reg(1);

tdijtag<=data_reg(1);

elsif(data_tms_counter="0011")then

tmsjtag<=addr_reg(2);

tdijtag<=data_reg(2);

elsif(data_tms_counter="0100")then

tmsjtag<=addr_reg(3);

tdijtag<=data_reg(3);

elsif(data_tms_counter="0101")then

tmsjtag<=addr_reg(4);

tdijtag<=data_reg(4);

elsif(data_tms_counter="0110")then